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CY8CLED16 ez-color? hb led controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-13105 rev. *h revised june 24, 2011 features hb led controller ? configurable dimmers support up to 16 independent led channels ? 8-to 32-bits of resolution per channel ? dynamic reconfiguration enables led controller plus other features: capsense ? , battery charging, and motor control visual embedded design ? led-based drivers ? binning compensation ? temperature feedback ? optical feedback ?dmx512 prism modulation technology? ? reduces radiated emi ? reduces low frequency blinking powerful harvard-architecture processor ? m8c processor speeds to 24 mhz ? 3.0 to 5.25 v operating voltage ? operating voltages down to 1.0 v using on-chip switch mode pump (smp) ? industrial temperature range: ?40 c to +85 c programmable pin configurations ? 25 ma sink, 10 ma source on all gpio ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpio ? up to eight analog inputs on gpio ? configurable interrupt on all gpio advanced peripherals (psoc ? blocks) ? 16 digital psoc blocks provide: ? 8-to 32-bit timers, counters, and pwms ? up to 4 full-duplex uarts ? multiple spi masters or slaves ? connectable to all gpio pins ? 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? complex peripherals by combining blocks flexible on-chip memory ? 32k flash program storage 50,000 erase/write cycles ? 2k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? electrically erasable programmable read-only memory ( eeprom) emulation in flash complete development tools ? free development software ? psoc designer? ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128 kb trace memory ez-color hb led controller preliminary data sheet
CY8CLED16 document number: 001-13105 rev. *h page 2 of 53 logic block diagram digital system sram 2k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32k digital block array two multiply accums. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog block array analog ref. analog input muxing i c 2 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 analog drivers system bus
CY8CLED16 document number: 001-13105 rev. *h page 3 of 53 contents ez-color? functional overview ..................................... 4 target applications ...................................................... 4 the psoc core ........................................................... 4 the digital system ...................................................... 4 the analog system ..................................................... 5 additional system resources ..................................... 6 ez-color device characterist ics ................................. 6 getting started .................................................................. 6 application notes ........................................................ 6 development kits ........................................................ 6 training ....................................................................... 6 cypros consultants .................................................... 6 solutions library .......................................................... 6 technical support ....................................................... 6 development tools .......................................................... 7 psoc designer software subsyst ems .......... .............. 7 designing with psoc designer ....................................... 8 select user modules ................................................... 8 configure user modules .............................................. 8 organize and connect .............. .............. ........... ......... 8 generate, verify, and debug ....................................... 8 pin information ................................................................. 9 pinouts ........................................................................ 9 register reference ......................................................... 11 register conventions ................................................ 11 register mapping tables .......................................... 11 electrical specifications ................................................ 14 absolute maximum ratings .... ................................... 15 operating temperature ............................................. 15 dc electrical characteristics ..................................... 16 ac electrical characteristics ..................................... 31 packaging information ................................................... 41 packaging dimensions .............................................. 41 thermal impedances ................................................. 42 capacitance on crystal pins .. ............. .............. ........ 42 solder reflow peak temperat ure ............................. 42 development tool selection .. .............. .............. ........... 43 software .................................................................... 43 evaluation tools ........................................................ 43 device programmers ............. .................................... 44 accessories (emulation and programming) .............. 44 ordering information ...................................................... 45 key device features ................................................. 45 ordering code definitions ..... .................................... 45 acronyms ........................................................................ 46 acronyms used ......................................................... 46 reference documents .................................................... 46 document conventions ......... .................................... 47 units of measure ....................................................... 47 numeric conventions ............ .................................... 47 glossary .......................................................................... 47 document history page ................................................. 52 sales, solutions, and legal information ...................... 53 worldwide sales and design s upport ......... .............. 53 products .................................................................... 53 psoc? solutions ...................................................... 53
CY8CLED16 document number: 001-13105 rev. *h page 4 of 53 ez-color? functional overview cypress's ez-color family of devices offers the ideal control solution for high brightness led applications requiring intel- ligent dimming control. ez-color devices combine the power and flexibility of programmable system-on-chip (psoc); with cypress's precise illumination signal modulation (prism) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. the ez-color family supports a range of independent led channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. this enables lighting designers the flexibility to choose the led array size and color quality. psoc designer software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and led binning compensation. ez-color's virtually limitless analog and digital customization allow for simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. these features, along with cypress' best-in-class quality and design support, make ez-color the ideal choice for intelligent hb led control applications. target applications lcd backlight large signs general lighting architectural lighting camera/cell phone flash flashlights the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a central processing unit (cpu), memory, clocks, and configurable general purpose i/o (gpio). the m8c cpu core is a powerful processor with speeds up to 48 mhz, providing a four million inst ructions per second (mips) 8-bit harvard-architecture microprocessor. the cpu utilizes an interrupt controller with 25 vect ors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watchdog timers (wdt). memory encompasses 32 kb of fl ash for program storage, 2 kb of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash ut ilizes four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the ez-color family incorporates flexible internal clock gener- ators, including a 24 mhz internal main oscillator (imo) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is desired, the 32.768 khz external crystal oscillator (eco) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system cl ock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the ez-color device. ez-color gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. the digital system the digital system is composed of 16 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit per ipherals, which are called user modules. digital peripheral configurations include those listed below. prism (8-to 32-bit) pwms (8-to 32-bit) pwms with dead band (8-to 32-bit) counters (8-to 32-bit) timers (8-to 32-bit) uart 8 bit with selectable parity (up to 4) spi master and slave (up to 4 each) i 2 c slave and multi-master (1 available as a system resource) cyclical redundancy checker/generator (8- to 32-bit) irda (up to 4) generators (8-to 32-bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by ez-color device family. this allows you the optimum choice of system resource s for your application. family resources are shown in ta b l e 1 on page 6.
CY8CLED16 document number: 001-13105 rev. *h page 5 of 53 figure 1. digital system block diagram the analog system the analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support spec ific application requirements. some of the more common ez-color analog functions (most available as user modules) are listed below. analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6- to 9-bit resolution) multiplying dacs (up to 4, with 6- to 9-bit resolution) high current output drivers (four with 40 ma drive as a core resource) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are provided in co lumns of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in the figure below. figure 2. analog system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row input configuration row output configuration row 2 dbb20 dbb21 dcb22 dcb23 4 4 row 0 dbb00 dbb01 dcb02 dcb03 4 4 row input configuration row output configuration row 3 dbb30 dbb31 dcb32 dcb33 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference
CY8CLED16 document number: 001-13105 rev. *h page 6 of 53 additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. resources include a multiplier, decimator, switch mode pump, low-voltage detection, and power-onreset (por). statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. multiply accumulate (mac) provid es fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. the decimator provides a custom hardware filter for digital signal, processing applications in cluding the creation of delta sigma adcs. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low-voltage-detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced power on reset (por) circuit eliminates the need for a system supervisor. an internal 1.3-voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch-mode pump (smp) generates normal operating voltages from a single 1.2-v battery cell, providing a low cost boost converter. ez-color device characteristics depending on your ez-color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6 , or 4 analog blocks. the following tabl e lists the resources available for specific ez-c olor device groups. th e device covered by thi s data sheet is shown in the highlighted row of the table. getting started the quickest way to understand the device is to read this data sheet and then use the psoc designer integrated development environment (ide). this data sheet is an overview of the ez-color integrated circuit and pr esents specific pin, register, and electrical specifications. for in depth information, along with detailed programming information, see the technical reference manual for this psoc device. for up-to-date ordering, packaging , and electrical specification information, see the latest device data sheets on the web at http://www.cypress.com . application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 1. ez-color device characteristics part number led channels digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size capsense cy8cled02 2 16 1 4 8 0 2 4 256 bytes 4k no cy8cled04 4 56 1 4 48 2 2 6 1k 16k yes cy8cled08 8 44 2 8 12 4 4 12 256 bytes 16k no CY8CLED16 16 44 4 16 12 4 4 12 2k 32k no
CY8CLED16 document number: 001-13105 rev. *h page 7 of 53 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/trans- mitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
CY8CLED16 document number: 001-13105 rev. *h page 8 of 53 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called ps oc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse with modulator (pwm) user modu le configures one or more digital psoc blocks, one for each ei ght bits of re solution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip -level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to -breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
CY8CLED16 document number: 001-13105 rev. *h page 9 of 53 pin information pinouts the CY8CLED16 device is available in three packages which are li sted and illustrated in the following tables. every port pin (l abeled with a ?p?) is capable of digital i/o. however, vss, v dd , smp, and xres are not capable of digital i/o. 28-pin part pinout table 2. 28-pin part pinout (ssop) pin no. type pin name description figure 3. 28-pin device digital analog 1 i/o i p0[7] analog column mux input. 2 i/o i/o p0[5] analog column mux input and column output. 3 i/o i/o p0[3] analog column mux input and column output. 4 i/o i p0[1] analog column mux input. 5 i/o p2[7] 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input. 8 i/o i p2[1] direct switched capacitor block input. 9 power smp switch mode pump (smp) connection to external components required. 10 i/o p1[7] i 2 c serial clock (scl). 11 i/o p1[5] i 2 c serial data (sda). 12 i/o p1[3] 13 i/o p1[1] crystal (xtalin), i 2 c serial clock (scl), issp-sclk [1] . 14 power vss ground connection. 15 i/o p1[0] crystal (xtalout), i 2 c serial data (sda), issp-sdata [1] . 16 i/o p1[2] 17 i/o p1[4] optional external clock input (extclk). 18 i/o p1[6] 19 input xres active high external reset with internal pull- down. 20 i/o i p2[0] direct switched capacitor block input. 21 i/o i p2[2] direct switched capacitor block input. 22 i/o p2[4] external analog ground (agnd). 23 i/o p2[6] external voltage reference (vref). 24 i/o i p0[0] analog column mux input. 25 i/o i/o p0[2] analog column mux input and column output. 26 i/o i/o p0[4] analog column mux input and column output. 27 i/o i p0[6] analog column mux input. 28 power v dd supply voltage. legend : a = analog, i = input, and o = output. a, i, p0[7] a, io, p0[5] a, io, p0[3] a, i, p0[1] p2[7] p2[5] a, i, p2[3] a, i, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref p2[4], external agnd p2[2], a, i p2[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 note 1. these are the issp pins, which are not high z at por.
CY8CLED16 document number: 001-13105 rev. *h page 10 of 53 table 3. 48-pin part pinout (qfn) [2] pin no. type pin name description figure 4. 48-pin device digital analog 1 i/o i p2[3] direct switched capacitor block input. 2 i/o i p2[1] direct switched capacitor block input. 3 i/o p4[7] 4 i/o p4[5] 5 i/o p4[3] 6 i/o p4[1] 7 power smp switch mode pump (smp) connection to external components required. 8 i/o p3[7] 9 i/o p3[5] 10 i/o p3[3] 11 i/o p3[1] 12 i/o p5[3] 13 i/o p5[1] 14 i/o p1[7] i 2 c serial clock (scl). 15 i/o p1[5] i 2 c serial data (sda). 16 i/o p1[3] 17 i/o p1[1] crystal (xtalin), i 2 c serial clock (scl), issp-sclk [1] . 18 power vss ground connection. 19 i/o p1[0] crystal (xtalout), i 2 c serial data (sda), issp-sdata [1] . 20 i/o p1[2] 21 i/o p1[4] optional external clock input (extclk). 22 i/o p1[6] 23 i/o p5[0] 24 i/o p5[2] 25 i/o p3[0] 26 i/o p3[2] 27 i/o p3[4] 28 i/o p3[6] 29 input xres active high external reset with internal pull-down. 30 i/o p4[0] 31 i/o p4[2] 32 i/o p4[4] 33 i/o p4[6] 34 i/o i p2[0] direct switched capacitor block input. 35 i/o i p2[2] direct switched capacitor block input. 36 i/o p2[4] external analog ground (agnd). 37 i/o p2[6] external voltage reference (vref). 38 i/o i p0[0] analog column mux input. 39 i/o i/o p0[2] analog column mux input and column output. 40 i/o i/o p0[4] analog column mux input and column output. 41 i/o i p0[6] analog column mux input. 42 power v dd supply voltage. 43 i/o i p0[7] analog column mux input. 44 i/o i/o p0[5] analog column mux input and column output. 45 i/o i/o p0[3] analog column mux input and column output. 46 i/o i p0[1] analog column mux input. 47 i/o p2[7] 48 i/o p2[5] legend : a = analog, i = input, and o = output. mlf (top view) p2[5] p2[7] p0[1], a, i p0[3], a, io p0[5], a, io p0[7], a, i vdd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref 10 11 12 a, i, p2[3] a, i, p2[1] p4[7] p4[5] p4[3] p4[1] smp p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[2], a, i p2[0], a, i p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] p2[4], external agnd 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2] note 2. the center pad on the qfn package should be connected to ground (vss) for best mechanical, thermal, and electrical performanc e. if not connected to ground, it should be electrically floated and no t connected to any other signal.
CY8CLED16 document number: 001-13105 rev. *h page 11 of 53 register reference register conventions abbreviations used the register conventions specific to this section are listed in the following table. register mapping tables this chapter lists the registers of the CY8CLED16 ez-color device. the device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks, bank 0 and bank 1. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
CY8CLED16 document number: 001-13105 rev. *h page 12 of 53 table 4. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) acces name addr (0,hex) acces prt0dr 00 rw dbb20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbb20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbb20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbb20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbb21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbb21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbb21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbb21cr0 47 # asd11cr3 87 rw c7 prt2dr 08 rw dcb22dr0 48 # asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw dcb22dr1 49 w asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw dcb22dr2 4a rw asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw dcb22cr0 4b # asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw dcb23dr0 4c # asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw dcb23dr1 4d w asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw dcb23dr2 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw dcb23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw dbb30dr0 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw dbb30dr1 51 w asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw dbb30dr2 52 rw asd20cr2 92 rw d2 prt4dm2 13 rw dbb30cr0 53 # asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw dbb31dr0 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw dbb31dr1 55 w asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw dbb31dr2 56 rw asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw dbb31cr0 57 # asc21cr3 97 rw i2c_scr d7 # prt6dr 18 rw dcb32dr0 58 # asd22cr0 98 rw i2c_dr d8 rw prt6ie 19 rw dcb32dr1 59 w asd22cr1 99 rw i2c_mscr d9 # prt6gs 1a rw dcb32dr2 5a rw asd22cr2 9a rw int_clr0 da rw prt6dm2 1b rw dcb32cr0 5b # asd22cr3 9b rw int_clr1 db rw prt7dr 1c rw dcb33dr0 5c # asc23cr0 9c rw int_clr2 dc rw prt7ie 1d rw dcb33dr1 5d w asc23cr1 9d rw int_clr3 dd rw prt7gs 1e rw dcb33dr2 5e rw asc23cr2 9e rw int_msk3 de rw prt7dm2 1f rw dcb33cr0 5f # asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
CY8CLED16 document number: 001-13105 rev. *h page 13 of 53 table 5. register map bank 1 table: configuration space name addr(1,hex) access name addr(1,hex) access name addr(1,hex) access name addr(1,hex) access prt0dm0 00 rw dbb20fn 40 rw asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw dbb20in 41 rw asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw dbb20ou 42 rw asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbb21fn 44 rw asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbb21in 45 rw asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbb21ou 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw dcb22fn 48 rw asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw dcb22in 49 rw asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw dcb22ou 4a rw asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw dcb23fn 4c rw asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw dcb23in 4d rw asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw dcb23ou 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw dbb30fn 50 rw asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw dbb30in 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw dbb30ou 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw dbb31fn 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw dbb31in 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw dbb31ou 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 prt6dm0 18 rw dcb32fn 58 rw asd22cr0 98 rw d8 prt6dm1 19 rw dcb32in 59 rw asd22cr1 99 rw d9 prt6ic0 1a rw dcb32ou 5a rw asd22cr2 9a rw da prt6ic1 1b rw 5b asd22cr3 9b rw db prt7dm0 1c rw dcb33fn 5c rw asc23cr0 9c rw dc prt7dm1 1d rw dcb33in 5d rw asc23cr1 9d rw osc_go_en dd rw prt7ic0 1e rw dcb33ou 5e rw asc23cr2 9e rw osc_cr4 de rw prt7ic1 1f rw 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 dec_cr2 e7 rw dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
CY8CLED16 document number: 001-13105 rev. *h page 14 of 53 electrical specifications this section presents the dc and ac electr ical specifications of the CY8CLED16 ez-color device. for the most up-to-date electri cal specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com . specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. refer to ta ble 20 for the electrical specifications for the internal main oscill ator (imo) using slimo mode. figure 5. voltage versus cpu frequency, and imo frequency trim options 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 slimo mode=1 v a l i d o p e r a t i n g re g i o n slimo mode=1 slimo mode=0
CY8CLED16 document number: 001-13105 rev. *h page 15 of 53 absolute maximum ratings operating temperature symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduces data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrade reliability. t baketemp bake temperature ? 125 see package label ? c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? v dd + 0.5 v i mio maximum current in to any port pin ?25 ? +50 ma i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma symbol description min typ max units notes t a ambient temperature ?0 ? +85 c t j junction temperature ?0 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances per package on page 42 . the user must limit the power consumption to comply with this requirement.
CY8CLED16 document number: 001-13105 rev. *h page 16 of 53 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 6. dc chip level specifications symbol description min typ max units notes v dd supply voltage 3.00 ? 5.25 v see dc por and lvd specifications, table 3-15 on page 27. i dd supply current ? 8 14 ma conditions are 5.0 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current ? 5 9 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i ddp supply current when imo = 6 mhz using slimo mode. ? 2 3 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 3 10 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, ?40c ?? t a ? 55 c. i sbh sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 4 25 ? a conditions are with internal slow speed oscillator, v dd = 3.3 v, 55 c < t a ? 85 c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, internal slow oscillator, and 32 khz crystal oscillator active. ? 4 12 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, ?40 c ? t a ? 55 c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and 32 khz crystal oscil- lator active. ? 5 27 ? a conditions are with properly loaded, 1 ? w max, 32.768 khz crystal. v dd = 3.3 v, 55 c < t a ? 85 c. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate v dd .
CY8CLED16 document number: 001-13105 rev. *h page 17 of 53 dc gpio specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 7. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd - 1.0 ? ? v ioh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. i oh high level source current 10 ? ? ma voh = v dd -1.0 v. see the limitations of the total current in the note for voh. i ol low level sink current 25 ? ? ma vol = 0.75 v. see the limitations of the total current in the note for vol. v il input low level ? ? 0.8 v v dd = 3.0 to 5.25. v ih input high level 2.1 ? v v dd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c . c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp =25 c.
CY8CLED16 document number: 001-13105 rev. *h page 18 of 53 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed spec ifications are measured in the anal og continuous time psoc block. ty pical parameters apply to 5 v at 25 c and are for design guidance only. table 8. 5-v dc operational amplifier specifications symbol description min typ max unit notes v osoa input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 1.6 1.6 1.6 1.6 1.6 1.6 10 10 10 10 10 10 mv mv mv mv mv mv ? tcv osoa average input offset voltage drift ? 4 23 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range (all cases, except power = high, opamp bias = high) common mode voltage range (power = high, opamp bias = high) 0 0.5 ? ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrroa common mode rejection ratio 60 ? ? db ? goloa open loop gain 80 ? ? db ? v ohighoa high output voltage swing (internal signals) v dd ? 0.01 ? ? v ? v olowoa low output voltage swing (internal signals) ? ? 0.1 v ? i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a ? psrr oa supply voltage rejection ratio 67 80 ? db v ss ? v in ? (v dd ? 2.25) or (v dd ? 1.25 v) ? v in ? v dd .
CY8CLED16 document number: 001-13105 rev. *h page 19 of 53 dc low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. table 9. 3.3-v dc operational amplifier specifications symbol description min typ max unit notes v osoa input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 1.4 1.4 1.4 1.4 1.4 ? 10 10 10 10 10 ? mv mv mv mv mv mv power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. tcv osoa average input offset voltage drift ? 7 40 v/c ? i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0 ? v dd v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrr oa common mode rejection ratio 60 ? ? db ? g oloa open loop gain 80 ? ? db ? v ohighoa high output voltage swing (internal signals) v dd ? 0.01 ? ? v ? v olowoa low output voltage swing (internal signals) ? ? 0.01 v ? i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? a a a a a a power = high, opamp bias = high setting is not allowed for 3.3 v v dd operation. psrr oa supply voltage rejection ratio 54 80 ? db v ss ? v in ? (v dd ? 2.25) or (v dd ? 1.25 v) ?? v in ? v dd table 10. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd - 1 v ? i slpc lpc supply current ? 10 40 ? a ? v oslpc lpc voltage offset ? 2.5 30 mv ?
CY8CLED16 document number: 001-13105 rev. *h page 20 of 53 dc analog output bu ffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 11. 5-v dc analog output buffer specifications symbol description min typ max unit notes v osob input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 3.2 3.2 3.2 3.2 18 18 18 18 mv mv mv mv ? tcv osob average input offset voltage drift ? 5.5 26 v/c ? v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v ? r outob output resistance power = low power = high ? ? ? ? 1 1 ? ? ? v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.3 0.5 v dd + 1.3 ? ? ? ? v v ? v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.3 0.5 v dd ? 1.3 v v ? i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma ? psrr ob supply voltage rejection ratio 40 64 db ? c l load capacitance ? ? 200 pf this specification applies to the external circuit driven by the analog output buffer. table 12. 3.3-v dc analog output buffer specifications symbol description min typ max unit notes v osob input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 3.2 3.2 6 6 20 20 25 25 mv mv mv mv high power setting is not recommended. tcv osob average input offset voltage drift power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 8 8 12 12 32 32 41 41 v/c v/c v/c v/c high power setting is not recommended. v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v ? r outob output resistance power = low power = high ? ? ? ? 10 10 w w ? v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 v dd + 1.0 0.5 v dd + 1.0 ? ? ? ? v v ? v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 v dd ? 1.0 0.5 v dd ? 1.0 v v ?
CY8CLED16 document number: 001-13105 rev. *h page 21 of 53 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. i sob supply current including bias cell (no load) power = low power = high ? ? 0.8 2.0 1 5 ma ma ? psrr ob supply voltage rejection ratio 60 64 ? db c l load capacitance ? ? 200 pf this specification applies to the external circuit driven by the analog output buffer. table 12. 3.3-v dc analog output buffer specifications (continued) symbol description min typ max unit notes table 13. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5v 5 v output voltage at v dd from pump 4.75 5.0 5.25 v configured as in note 3 . average, neglecting ripple. smp trip voltage is set to 5.0 v. v pump 3v 3 v output voltage at v dd from pump 3.00 3.25 3.60 v configured as in note 3 . average, neglecting ripple. smp trip voltage is set to 3.25 v. i pump available output current v bat = 1.5 v, v pump = 3.25 v v bat = 1.8 v, v pump = 5.0 v 8 5 ? ? ? ? ma ma configured as in note 3 . smp trip voltage is set to 3.25 v. smp trip voltage is set to 5.0 v. v bat 5v input voltage range from battery 1.8 ? 5.0 v configured as in note 3 . smp trip voltage is set to 5.0 v. v bat 3v input voltage range from battery 1.0 3? 3.3 v configured as in note 3 . smp trip voltage is set to 3.25 v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configured as in note 3 . 0 c ? t a ? 100. 1.25 v at t a = -40 c. ? v pump_line line regulation (over v bat range) ? 5 ? %v o configured as in note 3 . v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in table 17, ?dc por, smp, and lvd specifications,? on page 28 . ? v pump_load load regulation ? 5 ? %v o configured as in note 3 . v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in table 17, ?dc por, smp, and lvd specifications,? on page 28 . ? v pump_rippl e output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configured as in note 3 . load is 5 ma. e 3 efficiency 35 50 ? % configured as in note 3 . load is 5 ma. smp trip voltage is set to 3.25 v. f pump switching frequency ? 1.4 ? mhz ? dc pump switching duty cycle ? 50 ? % ? note 3. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 6.
CY8CLED16 document number: 001-13105 rev. *h page 22 of 53 figure 6. basic switch mode pump circuit dc analog reference specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. the guaranteed specific ations are measured throu gh the analog continuous ti me psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. battery c1 d1 + ez-color vdd vss smp v bat v pump l 1 table 14. 5-v dc analog reference specifications reference arf_cr[5:3] reference power settings symbol reference description min typ max unit 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.228 v dd /2 + 1.290 v dd /2 + 1.352 v v agnd agnd v dd /2 v dd /2 ? 0.078 v dd /2 ? 0.007 v dd /2 + 0.063 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.336 v dd /2 ? 1.295 v dd /2 ? 1.250 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.224 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.056 v dd /2 ? 0.005 v dd /2 + 0.043 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.298 v dd /2 ? 1.255 v refpower = med opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.057 v dd /2 ? 0.006 v dd /2 + 0.044 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.337 v dd /2 ? 1.298 v dd /2 ? 1.256 v refpower = med opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.294 v dd /2 + 1.359 v v agnd agnd v dd /2 v dd /2 ? 0.047 v dd /2 ? 0.004 v dd /2 + 0.035 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.299 v dd /2 ? 1.258 v
CY8CLED16 document number: 001-13105 rev. *h page 23 of 53 0b001 refpower = high opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.085 p2[4] + p2[6] ? 0.016 p2[4] + p2[6] + 0.044 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.055 v refpower = high opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.077 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.051 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.050 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.054 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.009 v dd v v agnd agnd v dd /2 v dd /2 ? 0.061 v dd /2 ? 0.006 v dd /2 + 0.047 v v reflo ref low v ss v ss v ss + 0.007 v ss + 0.028 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.039 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.049 v dd /2 ? 0.005 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.019 v refpower = med opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.054 v dd /2 ? 0.005 v dd /2 + 0.041 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = low v refhi ref high v dd v dd ? 0.042 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.046 v dd /2 ? 0.004 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v table 14. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CLED16 document number: 001-13105 rev. *h page 24 of 53 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.788 3.891 3.986 v v agnd agnd 2 bandgap 2.500 2.604 3.699 v v reflo ref low bandgap 1.257 1.306 1.359 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.792 3.893 3.982 v v agnd agnd 2 bandgap 2.518 2.602 2.692 v v reflo ref low bandgap 1.256 1.302 1.354 v refpower = med opamp bias = high v refhi ref high 3 bandgap 3.795 3.894 3.993 v v agnd agnd 2 bandgap 2.516 2.603 2.698 v v reflo ref low bandgap 1.256 1.303 1.353 v refpower = med opamp bias = low v refhi ref high 3 bandgap 3.792 3.895 3.986 v v agnd agnd 2 bandgap 2.522 2.602 2.685 v v reflo ref low bandgap 1.255 1.301 1.350 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.495 ? p2[6] 2.586 ? p2[6] 2.657 ? p2[6] v v agnd agnd 2 bandgap 2.502 2.604 2.719 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.531 ? p2[6] 2.611 ? p2[6] 2.681 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.500 ? p2[6] 2.591 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.519 2.602 2.693 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.530 ? p2[6] 2.605 ? p2[6] 2.666 ? p2[6] v refpower = med opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.503 ? p2[6] 2.592 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.517 2.603 2.698 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.529 ? p2[6] 2.606 ? p2[6] 2.665 ? p2[6] v refpower = med opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 ? p2[6] 2.594 ? p2[6] 2.665 ? p2[6] v v agnd agnd 2 bandgap 2.525 2.602 2.685 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.528 ? p2[6] 2.603 ? p2[6] 2.661 ? p2[6] v table 14. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CLED16 document number: 001-13105 rev. *h page 25 of 53 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.290 p2[4] + 1.343 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.295 p2[4] ? 1.254 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.226 p2[4] + 1.293 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.227 p2[4] + 1.294 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.295 p2[4] + 1.349 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.332 p2[4] ? 1.299 p2[4] ? 1.260 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.535 2.598 2.644 v v agnd agnd bandgap 1.227 1.305 1.398 v v reflo ref low v ss v ss v ss + 0.009 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.530 2.598 2.643 v v agnd agnd bandgap 1.244 1.303 1.370 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 2 bandgap 2.532 2.598 2.644 v v agnd agnd bandgap 1.239 1.304 1.380 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 2 bandgap 2.528 2.598 2.645 v v agnd agnd bandgap 1.249 1.302 1.362 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.041 4.155 4.234 v v agnd agnd 1.6 bandgap 1.998 2.083 2.183 v v reflo ref low v ss v ss v ss + 0.010 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.153 4.236 v v agnd agnd 1.6 bandgap 2.012 2.082 2.157 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 3.2 bandgap 4.049 4.154 4.238 v v agnd agnd 1.6 bandgap 2.008 2.083 2.165 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.154 4.238 v v agnd agnd 1.6 bandgap 2.016 2.081 2.150 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v table 14. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CLED16 document number: 001-13105 rev. *h page 26 of 53 table 15. 3.3-v dc analog reference specifications reference arf_cr[5:3] reference power settings symbol reference description min typ max unit 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.225 v dd /2 + 1.292 v dd /2 + 1.361 v v agnd agnd v dd /2 v dd /2 ? 0.067 v dd /2 ? 0.002 v dd /2 + 0.063 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.35 v dd /2 ? 1.293 v dd /2 ? 1.210 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.218 v dd /2 + 1.294 v dd /2 + 1.370 v v agnd agnd v dd /2 v dd /2 ? 0.038 v dd /2 ? 0.001 v dd /2 + 0.035 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.329 v dd /2 ? 1.296 v dd /2 ? 1.259 v refpower = med opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.221 v dd /2 + 1.294 v dd /2 + 1.366 v v agnd agnd v dd /2 v dd /2 ? 0.050 v dd /2 ? 0.002 v dd /2 + 0.046 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.331 v dd /2 ? 1.296 v dd /2 ? 1.260 v refpower = med opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.295 v dd /2 + 1.365 v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 ? 0.001 v dd /2 + 0.025 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.329 v dd /2 ? 1.297 v dd /2 ? 1.262 v 0b001 refpower = high opamp bias = high v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.098 p2[4] + p2[6] ? 0.018 p2[4] + p2[6] + 0.055 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.055 p2[4] ? p2[6] + 0.013 p2[4] ? p2[6] + 0.086 v refpower = high opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.082 p2[4] + p2[6] ? 0.011 p2[4] + p2[6] + 0.050 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.037 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.054 v refpower = med opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.079 p2[4] + p2[6] ? 0.012 p2[4] + p2[6] + 0.047 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.038 p2[4] ? p2[6] + 0.006 p2[4] ? p2[6] + 0.057 v refpower = med opamp bias = low v refhi ref high p2[4]+p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] + p2[6] ? 0.080 p2[4] + p2[6] ? 0.008 p2[4] + p2[6] + 0.055 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4]?p2[6] (p2[4] = v dd /2, p2[6] = 0.5 v) p2[4] ? p2[6] ? 0.032 p2[4] ? p2[6] + 0.003 p2[4] ? p2[6] + 0.042 v
CY8CLED16 document number: 001-13105 rev. *h page 27 of 53 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.06 v dd ? 0.010 v dd v v agnd agnd v dd /2 v dd /2 ? 0.05 v dd /2 ? 0.002 v dd /2 + 0.040 v v reflo ref low vss vss vss + 0.009 vss + 0.056 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.060 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.028 v dd /2 ? 0.001 v dd /2 + 0.025 v v reflo ref low vss vss vss + 0.005 vss + 0.034 v refpower = med opamp bias = high v refhi ref high v dd v dd ? 0.058 v dd ? 0.008 v dd v v agnd agnd v dd /2 v dd /2 ? 0.037 v dd /2 ? 0.002 v dd /2 + 0.033 v v reflo ref low vss vss vss + 0.007 vss + 0.046 v refpower = med opamp bias = low v refhi ref high v dd v dd ? 0.057 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.025 v dd /2 ? 0.001 v dd /2 + 0.022 v v reflo ref low vss vss vss + 0.004 vss + 0.030 v 0b011 all power settings. not allowed for 3.3 v ? ? ? ? ? ? ? 0b100 all power settings. not allowed for 3.3 v ? ? ? ? ? ? ? 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.213 p2[4] + 1.291 p2[4] + 1.367 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.333 p2[4] ? 1.294 p2[4] ? 1.208 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.217 p2[4] + 1.294 p2[4] + 1.368 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.320 p2[4] ? 1.296 p2[4] ? 1.261 v refpower = med opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.217 p2[4] + 1.294 p2[4] + 1.369 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.322 p2[4] ? 1.297 p2[4] ? 1.262 v refpower = med opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.219 p2[4] + 1.295 p2[4] + 1.37 v v agnd agnd p2[4] p2[4] p2[4] p2[4] v v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.324 p2[4] ? 1.297 p2[4] ? 1.262 v table 15. 3.3-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CLED16 document number: 001-13105 rev. *h page 28 of 53 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc por, smp, and lvd specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.507 2.598 2.698 v v agnd agnd bandgap 1.203 1.307 1.424 v v reflo ref low vss vss vss + 0.012 vss + 0.067 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.516 2.598 2.683 v v agnd agnd bandgap 1.241 1.303 1.376 v v reflo ref low vss vss vss + 0.007 vss + 0.040 v refpower = med opamp bias = high v refhi ref high 2 bandgap 2.510 2.599 2.693 v v agnd agnd bandgap 1.240 1.305 1.374 v v reflo ref low vss vss vss + 0.008 vss + 0.048 v refpower = med opamp bias = low v refhi ref high 2 bandgap 2.515 2.598 2.683 v v agnd agnd bandgap 1.258 1.302 1.355 v v reflo ref low vss vss vss + 0.005 vss + 0.03 v 0b111 all power settings. not allowed for 3.3 v. ? ? ? ? ? ? ? table 15. 3.3-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit table 16. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switched capacitor) ? 80 ? ff table 17. dc por, smp, and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r v dd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv notes 4. always greater than 50 mv above ppor (porlev = 00) for falling supply. 5. always greater than 50 mv above ppor (porlev = 10) for falling supply.
CY8CLED16 document number: 001-13105 rev. *h page 29 of 53 v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [4] 3.08 3.20 4.08 4.57 4.74 [5] 4.82 4.91 v v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for smp trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 v v v v v v v v v table 17. dc por, smp, and lvd specifications (continued) symbol description min typ max units notes
CY8CLED16 document number: 001-13105 rev. *h page 30 of 53 dc programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?-40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 18. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools. v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools. v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools. v ddiwrite supply voltage for flash write operation 3.15 ? 5.25 v this specification applies to this device when it is executing internal flash writes. i ddp supply current during programming or verify ? 10 30 ma v ilp input low-voltage during programming or verify ? ? 0.8 v v ihp input high-voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low-voltage during programming or verify ? ? vss + 0.75 v v ohv output high-voltage during programming or verify v dd - 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [6] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [7] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years notes 6. the 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. voltage ran ges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 7. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles eac h (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperat ure sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 8. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections.the i 2 c gpio pins also meet the mentioned specs. table 19. dc i 2 c specifications parameter description min typ max units notes v ili2c [8] input low level ? ? 0.3 v dd v 3.0 v ? v dd ?? 3.6 v ? ? 0.25 v dd v4.75 v ? v dd ?? 5.25 v v ihi2c [8] input high level 0.7 v dd ? ? v 3.0 v ?? v dd ?? 5.25 v
CY8CLED16 document number: 001-13105 rev. *h page 31 of 53 ac electrical characteristics ac chip level specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. note see the individual user module data sheets for info rmation on maximum frequencies for user modules. table 20. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 [9,10,11] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see the figure on page 19. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [9,10,11] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see the figure on page 19. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.0914 24 24.6 [9,10 ] mhz ? f cpu2 cpu frequency (3.3 v nominal) 0.0914 12 12.3 [10, 11] mhz ? f 48m digital psoc block frequency 0 48 49.2 [9,10,12] mhz refer to the ac digital block speci- fications below. f 24m digital psoc block frequency 0 24 24.6 [10,12 ] mhz ? f 32k1 internal low speed oscillator frequency 15 32 64 khz ? f 32k_u internal low speed oscillator untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on timing this. dc ilo internal low speed oscillator duty cycle 20 50 80 % ? f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency. t pllslew pll lock time 0.5 ? 10 ms ? t pllslewl ow pll lock time for low gain setting 0.5 ? 50 ms ? t os external crystal oscillator startup to 1% ? 250 500 ms ? t osacc external crystal oscillator startup to 100 ppm ? 300 600 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 ? w maximum drive level 32.768 khz crystal. 3.0v ? v dd ? 5.5 v, ?40 c ? t a ? 85 c. t xrst external reset pulse width 10 ? ? ? s ? dc24m 24 mhz duty cycle 40 50 60 % ? step24m 24 mhz trim step size ? 50 ? khz ? notes 9. 4.75 v < v dd < 5.25 v. 10. accuracy derived from internal main oscillator with appropriate trim for v dd range. 11. 3.0 v < v dd < 3.6 v. 12. see the individual user module data sheets for information on maximum frequencies for user modules. 13. refer to cypress jitter specifications application note, understanding datasheet jitter specificatio ns for cypress timing products ? an5054 for more information.
CY8CLED16 document number: 001-13105 rev. *h page 32 of 53 figure 7. pll lock timing diagram figure 8. pll lock for low gain setting timing diagram figure 9. external crystal oscillator startup timing diagram fout48m 48 mhz output frequency 46.8 48.0 49.2 [9, 11] mhz trimmed. utilizing factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz ? sr power_ up power supply slew rate ? ? 250 v/ms v dd slew rate during power up. t powerup time from end of por to cpu executing code ? 16 100 ms power up from 0v. see the system resets section of the psoc technical reference manual . tjit_imo [13] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 n = 32 24 mhz imo period jitter (rms) ? 100 400 ? tjit_pll [13] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 800 ps ? 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1200 n = 32 24 mhz imo period jitter (rms) ? 100 700 ? table 20. ac chip-level specifications (continued) symbol description min typ max units notes 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os
CY8CLED16 document number: 001-13105 rev. *h page 33 of 53 ac gpio specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 10. gpio timing diagram table 21. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.75 to 5.25 v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.75 to 5.25 v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 to 5.25 v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 to 5.25 v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin output voltage
CY8CLED16 document number: 001-13105 rev. *h page 34 of 53 ac operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v. table 22. 5-v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s ? t soa falling settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s ? sr roa rising slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s ? sr foa falling slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s ? bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz ? e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz ? table 23. 3.3-v ac operatio nal amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 ? s ? s ? t soa falling settling time to 0.1% of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 ? s ? s ? sr roa rising slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ ? s v/ ? s ? sr foa falling slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ ? s v/ ? s ? bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz ? e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz ?
CY8CLED16 document number: 001-13105 rev. *h page 35 of 53 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 11. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 12. typical opamp noise ? 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq (khz ) nv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl
CY8CLED16 document number: 001-13105 rev. *h page 36 of 53 ac low power comparator specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v at 25 c and are for design guidance only. ac digital block specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 24. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive comparator reference set within v reflpc . table 25. ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [14] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [14] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [14] ??ns disable mode 50 [14] ??ns input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2 spis input clock (sclk) frequency ? ? 4.1 mhz the input clock is the spi sclk in spis mode width of ss_negated between transmissions 50 [14] ??ns note 14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
CY8CLED16 document number: 001-13105 rev. *h page 37 of 53 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz table 25. ac digital block specifications (continued) function description min typ max unit notes table 26. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 4 4 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 3.4 3.4 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100pf load power = low power = high 0.55 0.55 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz
CY8CLED16 document number: 001-13105 rev. *h page 38 of 53 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temper ature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 27. 3.3v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 4.7 4.7 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100pf load power = low power = high ? ? ? ? 4 4 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100pf load power = low power = high .36 .36 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100pf load power = low power = high .4 .4 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz table 28. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? ? s table 29. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of t he external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? ? low period with cpu clock divide by 1 41.7 ? ?ns ? ? power up imo to switch 150 ? ? ? s?
CY8CLED16 document number: 001-13105 rev. *h page 39 of 53 ac programming specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 30. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns ? t fsclk fall time of sclk 1 ? 20 ns ? t ssclk data set up time to falling edge of sclk 40 ? ? ns ? t hsclk data hold time from falling edge of sclk 40 ? ? ns ? f sclk frequency of sclk 0 ? 8 mhz ? t eraseb flash erase time (block) ? 10 ? ms ? t write flash block write time ? 40 ? ms ? t dsclk data out delay from falling edge of sclk ? ? 45 ns v dd ? 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6 t eraseall flash erase time (bulk) ? 80 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 100 [15] ms 0c ? t j ? 100 c t program_cold flash block erase + flash block write time ? ? 200 [15] ms -40c ? t j ? 0 c note 15. for the full industrial range, the user must employ a temper ature sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information.
CY8CLED16 document number: 001-13105 rev. *h page 40 of 53 ac i 2 c specifications the following table lists guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75 v to 5.25 v and -40 c ? t a ? 85 c, or 3.0 v to 3.6 v and -40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. figure 13. definition for timing for fast-/standard-mode on the i 2 c bus table 31. ac characteristics of the i 2 c sda and scl pins symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz ? t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s? t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s? t highi2c high period of the scl clock 4.0 ?0.6 ? ? s? t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? ? s? t hddati2c data hold time 0 ?0 ? ? s? t sudati2c data set-up time 250 ?100 [16] ?ns ? t sustoi2c set-up time for stop condition 4.0 ?0.6 ? ? s? t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s? t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns ? i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition note 16. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sc l signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released.
CY8CLED16 document number: 001-13105 rev. *h page 41 of 53 packaging information this section illustrates the packaging specifications for the cy 8cled16 ez-color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip's footprint. for a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com . packaging dimensions figure 14. 28-pin (210-mil) ssop 51-85079 *e
CY8CLED16 document number: 001-13105 rev. *h page 42 of 53 figure 15. 48-pin (7 7 1.0 mm) qfn (sawn) important note for information on the preferred dimensions for mounting qfn pack ages, see the following application note "application notes fo r surface mount assembly of amkor's microleadframe (mlf) packages" available at h ttp://www.amkor.com. pinned vias for thermal conduction are not required for the low-power device. thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 7 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : s 5 ( ) 3 , 1 , ' 6 , ' ( 9 , ( : 5 + $ 7 & + $ 5 ( $ , 6 6 2 / ' ( 5 $ % / ( ( ; 3 2 6 ( ' 0 ( 7 $ / 5 ( ) ( 5 ( 1 & ( - ( ' ( & 0 2 $ / / ' , 0 ( 1 6 , 2 1 6 $ 5 ( , 1 0 , / / , 0 ( 7 ( 5 6 1 2 7 ( 6 3 $ & . $ * ( : ( , * + 7 j pad exposed solderable / $ 6 ( 5 0 $ 5 . s s 5 ( ) 5 ( ) 3 , 1 ' 2 7 6 ( $ 7 , 1 * 3 / $ 1 ( & s s s 3 , 7 & + 001-13191 *e table 32. thermal impedances per package package typical ? ja [17] 28 ssop 94 c/w 48 qfn [18] 28 c/w table 33. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf 48 qfn 1.8 pf notes 17. t j = t a + power x ? ja 18. to achieve the thermal impedance specifi ed for the qfn package, refer to "application notes for surface mount assembly of am kor's microleadframe (mlf) packages" available at http://www.amkor.com . table 34. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 c 30 s 48 qfn 260 c 30 s
CY8CLED16 document number: 001-13105 rev. *h page 43 of 53 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer psoc programmer is flexible and used on the bench in devel- opment. it is also suitable for factory programming. psoc programmer works either as a standalone programming appli- cation or operates directly from psoc designer. psoc programmer software is compatible with both psoc ice cube in-circuit emulator and psoc miniprog. it is available free of charge at http://www.cypress.com . evaluation tools all evaluation tools are sold at the cypress online store . cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers are sold at the cypress online store . cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs s pecial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable
CY8CLED16 document number: 001-13105 rev. *h page 44 of 53 accessories (emula tion and programming) table 35. emulation and programming accessories part no. pin package flex-pod kit [19] foot kit [20] adapter [21] CY8CLED16-28pvxi 28 ssop cy3250-led16 cy3250 -28ssop-fk adapters can be found at http://www.emulation.com . CY8CLED16-48lfxi 48 qfn cy3250-led16qfn cy3250-48qfn-fk notes 19. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 20. foot kit includes surface mount feet that can be soldered to the target pcb. 21. programming adapter converts non-dip package to dip footprin t. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com .
CY8CLED16 document number: 001-13105 rev. *h page 45 of 53 ordering information key device features the following table lists the CY8CLED16 ez-color de vices? key package features and ordering codes. ordering code definitions table 36. device key features and ordering information package ordering code flash (bytes) ram (bytes) switch mode pump temperature range digital psoc blocks analog psoc blocks digital i/o pins analog inputs analog outputs xres pin 28-pin (210 mil) ssop CY8CLED16-28pvxi 32 k 2 k yes ?40 ? c to +85 ? c 16 12 24 12 4 yes 28-pin (210 mil) ssop (tape and reel) CY8CLED16-28pvxit 32 k 2 k yes ?40 ? c to +85 ? c 16 12 24 12 4 yes 48-pin qfn (sawn) CY8CLED16-48ltxi 32 k 2 k yes ?40 ? c to +85 ? c 16 12 44 12 4 yes 48-pin qfn (tape and reel) (sawn) CY8CLED16-48ltxit 32 k 2 k yes ?40 ? c to +85 ? c 16 12 44 12 4 yes thermal rating: c = commercial e = extended cy 8 c led xx - xx xxxx i = industrial package type: px = pdip pb-free sx = soic pb-free pvx = ssop pb-free lfx/lkx/ltx/lqx/lcx = qfn pb-free ax = tqfp pb-free pin count part number led family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress
CY8CLED16 document number: 001-13105 rev. *h page 46 of 53 acronyms acronyms used ta b l e 3 7 lists the acronyms that are used in this document. reference documents design aids ? reading and writing psoc ? flash ? an2015 (001-40459) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 37. acronyms used in this datasheet acronym description acronym description ac alternating current mac multiply-accumulate adc analog-to-digital converter mips million instructions per second api application programming interface pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual-in-line package cpu central processing unit pll phase-locked loop crc cyclic redundancy check por power-on reset ct continuous time ppor precision power on reset dac digital-to-analog converter prs pseudo-random sequence dc direct current psoc ? programmable system-on-chip dtmf dual-tone multi-frequency pwm pulse-width modulator eco external crystal oscillator qfn quad flat no leads eeprom electrically erasable programmable read-only memory rtc real time clock gpio general purpose i/o sar successive approximation ice in-circuit emulator sc switched capacitor ide integrated development environment smp switch mode pump ilo internal low speed oscillator spi serial peripheral interface imo internal main oscillator sram static random access memory i/o input/output srom supervisory read only memory irda infrared data association ssop shrink small-outline package issp in-system serial programming uart universal asynchronous reciever / transmitter lcd liquid crystal display usb universal serial bus led light-emitting diode wdt watchdog timer lpc low power comparator xres external reset lvd low-voltage detect
CY8CLED16 document number: 001-13105 rev. *h page 47 of 53 document conventions units of measure ta b l e 3 8 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). nu mbers not indicated by an ?h?, ?b?, or 0x are decimals. table 38. units of measure symbol unit of measure symbol unit of measure db decibels ms milliseconds c degree celsius mh millihenry ff femtofarad ns nanoseconds khz kilohertz v microvolts k ? kilohm v volts mhz megahertz mv millivolts a microamperes w microwatts s microseconds % percent ma milliamperes w watt na nanoamperes mm millimeters pf picofarad ps picosecond pa pikoamperes ppm parts per million rt-hz root hertz nv nanovolts glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are switched capacitor (sc) and continuous time (ct) blocks. these blocks c an be interconnected to provide adcs, dacs, multi-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for progr ammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum.
CY8CLED16 document number: 001-13105 rev. *h page 48 of 53 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fixed fr equency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. glossary (continued)
CY8CLED16 document number: 001-13105 rev. *h page 49 of 53 digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmab le and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i 2 c is an inter-integrated circuit. it is used to connec t low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. glossary (continued)
CY8CLED16 document number: 001-13105 rev. *h page 50 of 53 master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. glossary (continued)
CY8CLED16 document number: 001-13105 rev. *h page 51 of 53 serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device that sequentially shif ts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory . the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three stat es: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued)
CY8CLED16 document number: 001-13105 rev. *h page 52 of 53 document history page document title: CY8CLED16 ez-color? hb led controller document number: 001-13105 revision ecn no origin of change submission date description of change ** 1148504 sfvtmp3 see ecn new document (revision **). *a 2763950 dpt 09/29/2009 added 48qfn package diagram (sawn). added saw marketing part number in ordering information. *b 2794355 xbm 10/28/2009 added ?contents? on page 3 updated ?development tools? on page 7. corrected fcpu1 and fc pu2 parameters in ?ac chip-level specifica- tions? on page 31. *c 2850593 fre 01/14/2010 updated dc gpio, ac chip-level, and ac programming specifications as follows: replaced tramp (time) with srpower_up (slew rate) specification. added note to flash endurance specification. added ioh, iol, dcilo, f32k_u, tpowerup, teraseall, tprogram_hot, and tprogram_cold specifications. corrected the pod kit part numbers. updated development tool selection . updated copyright and sales, solutions, and legal information urls. updated 28-pin ssop 48-pin qfn (punched), 48-pin qfn (sawn) package diagrams. removed preliminary for final status. *d 2896238 cgx 03/19/10 updated ordering information table. removed part numbers CY8CLED16-48lfxi and CY8CLED16-48lfxit updated copyright section. updated package diagram for spec 51-85061 *e 2903043 njf 04/01/2010 updated cypress website links added t baketemp and t baketime parameters removed reference to 2.4v removed sections ?third party tools? and ?build a psoc emulator? *f 3054665 cgx 10/11/2010 removed pruned parts CY8CLED16-48pvxi and CY8CLED16-48pvxit *g 3114959 njf 12/19/10 added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specification, removed existing jitter specifications. updated dc analog reference, dc operational amplifier specifications and dc analog output buffer specifications tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 12 since the labelling for y-axis was incorrect. removed footnote reference for ?solder reflow peak temperature? table. *h 3284932 shob 06/24/11 updated getting started , development tools , and designing with psoc designer . removed drawings and references to 48-pin qfn (punched) and 48-pin ssop. removed obsolete kits. removed reference to obsolete spec an2012.
document number: 001-13105 rev. *h revised june 24, 2011 page 53 of 53 psoc designer? and ez-color? are trademarks and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. CY8CLED16 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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